1. Field of the Invention
The present invention relates to a debugging support device, debugging support method, and program thereof. In particular, the present invention relates to a debugging support device, debugging support method, and program thereof for programs to be executed in parallel.
2. Description of Related Art
Conventionally, multi-core processor systems having a plurality of cores have been widely used. There are cases where a multi-core processor system takes the form of a parallel computer in which each of the cores included in the system has a cache memory. In a multi-core processor system, the consistency in values is maintained by hardware (hereinafter abbreviated as HW) or software (hereinafter abbreviated as SW).
In particular, in the case of a system where consistency is maintained by SW, a memory space is divided into pages, whereby each core executes respective processing while managing pages related to such processing in a shared state or an exclusive state.
For example, let us assume a case of a parallel computer in which two cores, namely, 1 and 2 respectively include a computing unit and a cache memory, and process data contained in a single main memory connected to the cores 1 and 2 via a bus. The memory space is divided into pages, whereby pages related to processing are set to either a shared state or an exclusive state when a program is executed by each core.
For example, assume that, at a given moment, a given page “a” is set to a shared state so as to enable data thereof to be shared among cores, and a given page “b” is set to an exclusive state so as to enable a particular core to write data thereinto. Since the page “a” set to the shared state is to be shared among cores, the page “a” is set so as to be readable from any core but, at the same time, unwriteable by any core.
Because the page “a” is in a shared state, the same value such as y is read by both the core 1 and the core 2 when reading a value from a given line in page “a”. In the shared state, the core 1 and the core 2 are prohibited from writing a value to the page “a”. This is because if core 1 writes a given value such as z to the line, the core 2 is unable to see the updated value and ends up reading the old value y, thereby preventing consistency from being maintained.
The page “b” in an exclusive state is to be exclusively used by a specific core that has become the so-called owner of the page “b”. Therefore, only the specific core is able to read from and write to the page “b”.
Since the page “b” is set to an exclusive state by the core 1, the core 1 is able to read from and write to each line in the page “b”. In addition, no problem will arise even if the value y on the main memory and the value z in the cache memory of the core 1 are inconsistent. This is because only the core 1 can read data on the page “b”. Furthermore, the inconsistent state problem can be solved by having the core 1 write back to the memory when releasing the page “b”. When the page “b” is in an exclusive state, the core 2 is prohibited from both reading and writing data from/to the page “b”. This is because when attempting to read data, there is a risk that an old value will be inadvertently read. Moreover, when data is mistakenly written, there is a risk that the core 1 will overwrite the written value with another value.
Access to each page is restricted in accordance with such states, and the states dynamically change during program execution.
Various techniques for debugging software, including inconsistencies thereof, to be executed by such a multi-core processor system are being proposed. Normally, when debugging software, a code for monitoring is added to a debugging target program in order to monitor operations inside the cores. Such added codes enable observation of operational states inside the core in accordance with the target program.
Japanese Patent Application Laid-Open Publication No. 2006-146412 proposes a multi-core processor with a built-in debugging control unit, in which the debugging control unit is controlled by a single CPU. In addition, Japanese Patent Application Laid-Open Publication No. 05-165675 proposes a debugging support device capable of monitoring program access by a plurality of processors to respective memory regions.
However, when a monitoring code is added to a debugging target program, the increase in executable codes caused by the addition creates a problem that the difference in respective execution timings and the like between a case where a program to which the monitoring code has not been added is executed and a case where a program to which the monitoring code has been added is executed prevents debugging from being performed accurately. For example, there may be a case where the execution of the program to which the monitoring code has not been added results in a bug but the execution of the program to which the monitoring code has been added does not.
In particular, in the case of a multi-core processor system, debugging requires that focus be placed on a plurality of cores, the behavior of each core be monitored, and an analysis for bug detection must be performed.
However, while the techniques according to the proposals described above are capable of monitoring data associated with behavior, information regarding bugs cannot be accurately detected. In addition, the proposals do not particularly involve a method of presenting bug-related information to a program developer and the like in an easily-understood manner.
On the other hand, in a system that does not include HW for managing shared resources such as a memory, it is required that the occupancy state of resources be managed by having a program developer embed a call code for occupancy state transition processing of resources in SW into the target program. For example, Japanese Patent Application Laid-Open Publication No. 2008-517370 and U.S. Patent Publication 2006-0259698 A1 propose targeting cache coherence violation detection of a shared memory as a method for detecting a rule violation of resource management processing and presenting the same to a program developer. However, with the proposals, it is difficult to identify the cause of a violation when occupancy state transition processing is called by a plurality of processing units operating in parallel.
Furthermore, for example, while Japanese Patent Application Laid-Open Publication No. 2008-4054 proposes a technique for graphically representing task transition states and resource use states in a time sequence and utilizing the same to improve performance as a method of displaying shared resource use states of a plurality of processing units that operate in parallel, the graphically represented states cannot be utilized for detecting rule violations.
Moreover, besides the consistency problem described above, a multi-core processor system has problems in exclusive control of performance regarding lock or unlock instructions, occurrences of deadlocks, and the like.
Consequently, including the aforementioned problems, no proposals have been made in regard to a method of accurately detecting bug-related information and notifying a program developer or the like of such bug-related information in an easily-understood manner.